This invention relates to capacitor structures for metal-oxide-semiconductors (MOS), and in particular, to a multilayer pillar array capacitor structure for deep sub-micron complementary MOS (CMOS).
Conventional capacitor structures for deep sub-micron CMOS are typically constructed with two flat parallel plates separated by a thin dielectric layer. The plates are formed by layers of conductive material, such as metal or polysilicon. The capacitor structure is usually isolated from the substrate by an underlying dielectric layer. To achieve high capacitance density in these structures, additional plates are provided. FIG. 1 illustrates a conventional multilayer parallel plate capacitor structure 10 in a deep sub-micron CMOS. The capacitor structure 10 includes a vertical stack of electrically conductive lines 12 separated by dielectric layers 13. The conductive lines 12 and dielectric layers 13 are constructed over a semiconductor substrate 11. The conductive lines 12 form the plates or electrodes of the capacitor 10. The plates 12 are electrically connected together in an alternating manner such that all the xe2x80x9cAxe2x80x9d plates are of a first polarity and all the xe2x80x9cBxe2x80x9d plates are of a second polarity, opposite to the first polarity.
A major limitation associated with parallel plate capacitor structures is that the minimum distance between the plates does not change as geometries in CMOS processes are scaled down. Hence, gains in capacitance density are not realized during such down scaling.
Various other capacitor structures with high capacitance densities, such as double polysilicon capacitors and gate-oxide capacitors, are known in the art. Double polysilicon capacitors, however, do not lend themselves to deep sub-micron CMOS processes. Gate-oxide capacitors are generally not used in deep sub-micron CMOS processes because they have large gate areas which cause yield and reliability issues, they generate capacitances which vary with voltage, and may experience high voltages that can breakdown the gate-oxide.
Trench capacitor structures for dynamic random access memories (DRAMs) have high capacitance densities. Such capacitors are formed by etching a trench in the substrate and filling the trench with conductive and dielectric material to form a vertical capacitance structure. However, trench capacitors are costly to fabricated because they add etching and trench filling processes.
Interdigitated capacitor structures are used in microwave applications. These capacitors have closely placed, interdigitated conductive line structures which produce fringing and cross-over capacitances therebetween to achieve capacitance. However, the cross-over capacitance produced by interdigitated capacitors is limited to a single conductor level.
Accordingly, a need exists for an improved capacitor structure for deep sub-micron CMOS structures, having a high capacitance density which increases with shrinking semiconductor process geometries.
A capacitor structure, especially for use in deep sub-micron CMOS, comprising an array of electrically conductive pillars which form the plates of the capacitor. Each of the pillars is formed by electrically conductive lines segments from at least two different conductor levels electrically connected by an electrically conductive via. Dielectric material is disposed between the two conductor levels and the pillars of the array. The pillars are electrically connected to opposing nodes in an alternating manner so that the pillars are electrically interdigitated.